Motorola MVME2400 Series Manuale di Servizio Scaricare il pdf (Pagina 53)

ISA Local Resource Bus

http://www.mcg.mot.com/literature 1-33

SET_SIG0 Writing a 1 to this bit will set the SIG0 status bit.

SET_LM1 Writing a 1 to this bit will set the LM1 status bit.

SET_LM0 Writing a 1 to this bit will set the LM0 status bit.

CLR_SIG1Writing a 1 to this bit will clear the SIG1 status bit.

CLR_SIG0Writing a 1 to this bit will clear the SIG0 status bit.

CLR_LM1 Writing a 1 to this bit will clear the LM1 status bit.

CLR_LM0 Writing a 1 to this bit will clear the LM0 status bit.

LM/SIG Status Register

The LM/SIG Status Register is an 8-bit register located at ISA I/O address

x1001. This register, in conjunction with the LM/SIG Control Register,

provides a method to generate interrupts. The Universe II ASIC is

programmed so that this register can be accessed from the VMEbus to

provide a capability to generate software interrupts to the onboard

processor(s) from the VMEbus.

EN_SIG1 When the EN_SIG1 bit is set, a LM/SIG Interrupt 1 is

generated if the SIG1 bit is asserted.

EN_SIG0 When the EN_SIG0 bit is set, a LM/SIG Interrupt 0 is

generated if the SIG0 bit is asserted.

EN_LM1 When the EN_LM1 bit is set, a LM/SIG Interrupt 1 is

generated and the LM1 bit is asserted.

REG LM/SIG Status Register - Offset $1001

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

FIELD EN

SIG1

SIG0

LM1

LM0

SIG1 SIG0 LM1 LM0

OPER R/W READ-ONLY

RESET 00000000

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Motorola MVME2400 Series Manuale di Servizio Pagina 53