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3-54 Computer Group Literature Center Web Site

System Memory Controller (SMC)

ROM A Base/Size Register

Writes to this register must be enveloped by a period of time in which no

accesses to ROM/Flash Block A, occur. A simple way to provide the

envelope is to perform at least two accesses to this or another of the SMC’s

registers before and after the write.

ROM A BASE

These control bits define the base address for ROM/Flash

Block A. ROM A BASE

bits 0-11 correspond to

PowerPC 60x address bits 0 - 11 respectively. For larger

ROM/Flash sizes, the lower significant bits of ROM A

BASE are ignored. This means that the block’s base

address will always appear at an even multiple of its size.

ROM A BASE

is initialized to $FF0 at power-up or local

bus reset.

Note that in addition to the programmed address, the first

1Mbyte of Block A also appears at $FFF00000 -

$FFFFFFFF if the rom_a_rv

bit is set and the rom_b_rv

bit is cleared.

Also note that the combination of ROM_A_BASE

and

rom_a_siz

should never be programmed such that

ROM/Flash Block A responds at the same address as the

CSR, SDRAM, External Register Set, or any other slave

on the PowerPC bus.

rom_a_64 rom_a_64 indicates the width of ROM/Flash being used

for Block A. When rom_a_64 is cleared, Block A is 16

bits wide, where each half of SMC interfaces to 8 bits.

ADDRESS

$FEF80050

BIT

NAME

ROM A BASE

rom_a_64

rom a siz0

rom a siz1

rom a siz2

rom_a_rv

rom a en

rom a we

OPERATIO

READ/WRITE

R/W

READ ZERO

R/W

RESET

$FF0 PL

V P

0 PL

V P

0 PL

1 2 ... 235 236 237 238 239 240 241 242 243 244 245 ... 353 354

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Motorola MVME2400 Series Manuale di Servizio Pagina 240

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