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Instruction Set Summary

3-24 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

3.5.1 Intermediate Result

All FPU calculations use an intermediate result. When the FPU performs any operation, the

calculation is carried out using extended-precision inputs, and the intermediate result is

calculated as if to produce inﬁnite precision. After the calculation is complete, the

intermediate result is rounded to the selected precision and stored in the destination.

Figure 3-1 illustrates the intermediate result format. The intermediate result’s exponent for

some dyadic operations (i.e., multiply and divide) can easily overﬂow or underﬂow the 15-

bit exponent of the designation ﬂoating-point register. To simplify the overﬂow and underﬂow

detection, intermediate results in the FPU maintain a 16-bit (17 bits for the MC68881 and

MC68882), twos complement, integer exponent. Detection of an overﬂow or underﬂow

intermediate result always converts the 16-bit exponent into a 15-bit biased exponent before

being stored in a ﬂoating-point data register. The FPU internally maintains the 67-bit

mantissa for rounding purposes. The mantissa is always rounded to 64 bits (or less,

depending on the selected rounding precision) before it is stored in a ﬂoating-point data

If the destination is a ﬂoating-point data register, the result is in the extended-precision

format and is rounded to the precision speciﬁed by the FPSR PREC bits before being stored.

All mantissa bits beyond the selected precision are zero. If the single- or double-precision

mode is selected, the exponent value is in the correct range even if it is stored in extended-

precision format. If the destination is a memory location, the FPSR PREC bits are ignored.

In this case, a number in the extended-precision format is taken from the source ﬂoating-

point data register, rounded to the destination format precision, and then written to memory.

Depending on the selected rounding mode or destination data format in effect, the location

of the least signiﬁcant bit of the mantissa and the locations of the guard, round, and sticky

bits in the 67-bit intermediate result mantissa varies. The guard and round bits are always

calculated exactly. The sticky bit is used to create the illusion of an inﬁnitely wide

intermediate result. As the arrow illustrates in Figure 3-1, the sticky bit is the logical OR of

all the bits in the inﬁnitely precise result to the right of the round bit. During the calculation

stage of an arithmetic operation, any non-zero bits generated that are to the right of the

round bit set the sticky bit to one. Because of the sticky bit, the rounded intermediate result

for all required IEEE arithmetic operations in the RN mode is in error by no more than one

half unit in the last place.

Figure 3-1. Intermediate Result Format

16-BIT EXPONENT

63-BIT MANTISSA

LSB OF FRACTION

GUARD BIT

ROUND BIT

STICKY BIT

INTEGER BIT

OVERFLOW BIT

1 2 ... 90 91 92 93 94 95 96 97 98 99 100 ... 645 646

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Motorola CPU32 Manuale Utente Pagina 95