Motorola CPCI-6115 Manuale di Servizio Pagina 134

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CPX8216 and CPX8216T Installation and Use (6806800A52C)
Chapter 10 Pin Assignments
114
10 GND _AD13 _+5 _AD12 _AD11 _AD10 GND
9 GND _PAR _CBE1# _AD15
_GND _AD14 GND
8GND_STOP#
_+5 _LOCK# _PERR# _SERR# GND
7 GND _FRAME# _IRDY# _TRDY#
_GND _DEVSEL# GND
6GND_AD18
_+5 _AD17 _AD16 CBE2# GND
5 GND _AD21 _CLK _AD20
_GND _AD19 GND
4 GND _CBE3#
_+5 _IDSEL _AD23 _AD22 GND
3 GND _AD28 _AD27 _AD26 _AD25 _AD24 GND
2 GND _GNT# _REQ# _AD31 _AD30 _AD29 GND
1 GND _INTA# _INTB# _INTC# _INTD# _RST# GND
Table 10-17. P4 Connector, HSC Slots 8 and 10
POS
Row
Z
Row A Row B Row C Row D Row E Row F
25 NP SGA4 SGA3 SGA2 SGA1 SGA0 FG
24 NP GA4 GA3 GA2 GA1 GA0 FG
23 NP +12V CT_RST[n]# CT_EN[n]# -12V CT_MC FG
22 NP PSF0# RSVD RSVD RSVD RSVD FG
21 NP -SELVbat PSF1# RSVD RSVD SELVbat RTN FG
20 NP NP NP NP NP NP NP
19 NP NP NP NP NP NP NP
18 NP VRG NP NP NP VRG RTN NP
17 NP NP NP NP NP NP NP
16 NP NP NP NP NP NP NP
15 NP -Vbat NP NP NP Vbat RTN NP
NP=Not Populated. P4 implements the full H.110 Bus connections, which requires P4 to use
depopulated connectors.
CT_RST1# through CT_RST6# are routed radially to the bridge slots.
CT_EN1# is connected to BD_SEL1# on the backplane, and so forth.
[n]=n is the slot number.
Refer to the H.110 specifications for line terminations.
Table 10-16. P5 Connector, HSC/Bridge (Slots 8 and 10) (continued)
POS Row Z Row A Row B Row C Row D Row E Row F
The _GND, _+5 and _+3 in the shaded cells are provided by the CPU board; they are not connected
to the chassis power plane. These signals are prefixed with CPUA if the board resides in slot 10 or
CPUB if the board resides in slot 8 (for example, CPUA_+5).
Unshaded signals beginning with an underscore (_) are prefixed with the local PCI bus name:
*For boards located in slot 10 (Domain A), the signal name is prefixed with L_PCI_A (for example,
L_PCI_A_AD17).
*For boards located in slot 8 (Domain B), the signal name is prefixed with L_PCI_B (for example,
L_PCI_B_AD17).
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