Motorola MVME1X7P manuali

Motorola MVME1X7P Manuale Utente (316 pagine)

Marchio: Motorola | Categoria: Hardware | Dimensione: 2.86 MB |

Inglese

Indice

Programmer’s Reference

1

Safety Summary

3

Flammability

4

EMI Caution

4

Lithium Battery Caution

4

Contents

7

List of Figures

17

List of Tables

19

About This Manual

21

Overview of Contents

22

Comments and Suggestions

22

1Programming Issues

27

Programming Issues

28

Applicable Industry Standards

30

Block Diagram

30

Introduction

31

Programming Interfaces

33

EEPROMs on the MVME1X7P

34

Flash Memory on the MVME177

35

Onboard SDRAM

37

VMEbus Interface

38

I/O Interfaces

38

Local Resources

42

VMEbus Interface and VMEchip2

44

RESET switch control

45

Memory Maps

46

DRAMSIZE

47

4MB Flash

47

Detailed I/O Memory Maps

51

1514131211109876543210

56

Register Bit Names

60

Size Access

62

VMEbus Memory Map

72

Interrupt Handling

73

1. Set up Tick Timer:

74

Cache Coherency (MVME167P)

75

Cache Coherency (MVME177P)

76

Using Bus Timers

77

Indivisible Cycles

78

Sources of Local Bus Errors

80

Error Conditions

81

MPU Parity Error

82

MPU Offboard Error

82

MPU TEA - Cause Unidentified

82

MPU Local Bus Time-out

83

DMAC VMEbus Error

83

DMAC Parity Error

83

DMAC Offboard Error

84

DMAC LTO Error

84

DMAC TEA - Cause Unidentified

85

SCC Retry Error

85

SCC Parity Error

86

SCC Offboard Error

86

SCC LTO Error

87

LAN Parity Error

87

LAN Offboard Error

87

LAN LTO Error

88

SCSI Parity Error

88

SCSI Offboard Error

88

SCSI LTO Error

89

2VMEchip2

91

VMEbus-to-Local-Bus Interface

99

VMEchip2

100

Functional Blocks

101

Tick and Watchdog Timers

104

VMEbus Interrupter

106

VMEbus System Controller

107

LCSR Programming Model

110

OPER R/W

119

WAIT RMW

143

LVFAIR LVRWD

144

RESET switch is disabled

160

WDBFE WDS/L WDRSE

161

ABORT switch

186

ABORT switch is depressed

186

GPOEN3 GPOEN2 GPOEN1 GPOEN0

186

GPIOO3 GPIOO2 GPIOO1 GPIOO0

187

GCSR Programming Model

190

Programming the GCSR

192

Bit Numbers

193

3PCCchip2

199

General Description

200

BBRAM Interface

201

PCCchip2

202

Functional Description

203

Parallel Port Interface

204

General Purpose I/O Pin

205

CD2401 SCC Interface

205

Tick Timer

207

Overall Memory Map

208

Programming Model

209

Chip ID Register

212

Chip Revision Register

212

General Control Register

213

Vector Base Register

214

Programming the Tick Timers

216

Programming the Printer Port

237

Interrupt Mask Level Register

247

4MCECC Functions

249

Features

250

Cache Coherency

252

MCECC Functions

254

Error Logging

256

Arbitration

257

Chip Defaults

257

Memory Configuration Register

262

Base Address Register

263

DRAM Control Register

263

BCLK Frequency Register

264

Data Control Register

265

Scrub Control Register

267

Chip Prescaler Counter

269

STON2-STON0

270

Error Logger Register

275

Error Address (Bits 31-24)

276

Error Address (Bits 23-16)

276

Error Address (Bits 15-8)

277

Error Address (Bits 7-4)

277

Error Syndrome Register

278

Defaults Register 1

278

Defaults Register 2

280

SDRAM Configuration Register

281

Initialization

282

Syndrome Decoding

284

ASummary of Changes

287

Summary of Changes

288

BPrinter and Serial Port

289

Connections

289

1347 9403

290

Connection Diagrams

291

1349 9403

292

1351 9403

294

1353 9403

296

1355 9403

298

CRelated Documentation

299

Manufacturers’ Documents

300

Related Specifications

301

Related Documentation

302

Document Title and Source

302

Publication

302

Numerics

303

Register 1 2-29

315

Register 2 2-31

315

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